Schematic Spreadsheet Design for Field Programmable Gate Arrays
Senior Project: 1996-1997
Field Programmable Gate Arrays (FPGAs) have been around since Xilinx introduced
the XC2064 in the mid-1980s. Unlike the PALs (AND - OR arrays with limited OR
terms), developed earlier, Xilinx FPGAs consisted of a matrix of logic cells
surrounded by vertical and horizontal channels of programmable interconnects.
Each cell could be programmed with any arbitrary logic function of the limited
number of cell inputs.
The Xilinx FPGAs became popular because they were capable of any logical
function and, unlike PALs, they could be scaled to larger and larger arrays.
However, the early users had to partition the logic and route the interconnects
in addition to defining the logic. This was a new skill for these users. It was
difficult to obtain efficient (or even working) designs and caused a lot of
disenchantment. Xilinx responded by developing more automated methods to
partition, place, and route designs entered via schematics or other means.
These automated methods were wildly inefficient in logic density and circuit
performance. These techniques could not match the efficiency of a skilled FPGA
designer.
In response to this situation, Rhodes Press developed the concept of "Schematic
Spreadsheet", which consists of an algorithm to generate a "die-layout
background sheet" in a schematic capture CAD program, a means to efficiently
generate modules of standard logic functions that can be easily placed on the
die-layout background sheet, and finally, an algorithm that extracts the
placement information from the schematic elements and passes these attributes
to the "fitting" program.
This project required development of a digital database of scanned, published
size and I/O location information; development of an algorithm to generate an
arbitrary die-layout background sheet for any part type; development of an
algorithm to place logic modules in cell locations on the die-layout background
sheet; and development of an algorithm to extract placement information from
the schematic elements and attach that placement information to the schematic
file. The project was implemented in C in an MS-DOS environment.


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