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Colloquium - Vachharajani

Keeping up with Moore's Law: Software Tools for Multi-Core Systems
Department of Electrical and Computer Engineering

For years, the steadily growing transistor count in new single processor systems has consistently delivered increased performance for a wide range of applications. Unfortunately, the techniques used to turn these transistors into application performance, such as frequency scaling, speculation, and caching, are now showing greatly diminished returns. This has happened primarily due to limitations arising from power consumption, design complexity, and wire delays. In response, designers have turned to chip multiprocessors (CMPs) that incorporate multiple processor cores on a single die.

While these CMPs are a boon to throughput driven applications such as web servers, single-threaded application performance remains stagnant as only parallel programs can harness modern CMP designs. To make matters worse, traditional approaches to parallelizing software are not accessible to most programmers. Without a set of tools to make parallel programming accessible to everyday programmers, the performance improvements that have advanced almost every field in the last 20 years, from genetics to finance, will stop or slow dramatically.

This talk will discuss a variety of research that aims to produce tools to help programmers exploit the performance potential of modern chip-multiprocessor (CMP) designs. The talk will begin with an overview of why designers have moved to CMP designs, then discuss why ordinary programs cannot leverage these designs, and then finally discuss our initial approaches to solving the challenge that these systems pose. Topics will range from identifying parallelism for CMPs, to extracting performance from parallelism on CMPs, to validating the correctness of parallel programs. The talk will present enough background to be accessible to most technical audiences but will have enough depth to interest those with expertise in the area.

Manish Vachharajani completed his PhD at Princeton University in 2004 where he played a key role in developing the , a tool for highly accurate high-level modeling of hardware designs and the development of various compiler technologies. His work has been recognized by several best paper awards and an Intel Foundation Graduate Fellowship. Since August 2004, he has been with the Department of Electrical and Computer Engineering at the University of Colorado Boulder. His work spans the areas of software analysis, computer architecture, operating systems, and software validation.

This talk is sponsored by the Department of Electrical and Computer Engineering.

Department of Computer Science
University of Colorado Boulder
Boulder, CO 80309-0430 USA
May 5, 2012 (14:13)