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Colloquium - Tune

Critical-Path Aware Processor Architectures
Eric Tune
University of California, San Diego
4/20/2004
3:30pm-4:30pm

Modern microprocessors can perform several operations in parallel, out of program order. As a result, the execution time of the program is determined by a small subset of all dynamic instructions. The dependencies between these instructions comprise the critical path of the program.

However, current processors treat all instructions equally when allocating limited hardware resources. We propose replacing egalitarian policies with critical-path aware policies, which optimize only critical instructions, and which exploit the scheduling slack of non-critical instructions. We demonstrate that simple hardware mechanisms can predict which instructions are on the critical path with sufficient accuracy to allow for significant improvements in performance when critical-path aware policies are applied to processor designs with clustered pipelines, with multi-speed functional units, and with value prediction. We also suggest releasing unused resources held by non-critical instructions in multithreaded processors, resulting in a design with 65% more throughput and requiring only minor changes to hardware.

Eric Tune is a PhD Candidate in Computer Engineering at the University of California at San Diego. He is interested in Computer Architecture. He also holds BS and MS degrees in Computer Engineering from the University of California at San Diego.

Sponsored by the Department of Electrical and Computer Engineering.

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University of Colorado Boulder
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