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Colloquium - Chong

Architectural Issues in Scalable Quantum Computing
Quantum Architecture Research Center, University of California at Davis
2/13/2003
3:30pm-4:30pm

Computing with quantum states has become an increasingly intriguing reality. Prototype quantum computers of 5 to 7 bits have begun to appear using molecules in solution and photon traps. For true scalability and to exploit our tremendous historical investment in silicon, however, solid-state silicon quantum implementations are needed.

This talk begins with some background in quantum computing. I then focus on two fundamental issues in future architectures. First, the movement of quantum data on silicon. Second, reducing the overhead of error correction to cope with environmental noise.

We propose a novel approach to low-latency, reliable communication through a "quantum wire" architecture that uses teleportation of error-coded quantum bits. I discuss the architectural building blocks for quantum wires and quantum computation in general. I further discuss quantum error correction codes and how to reduce their overhead. I conclude with some work that exploits both quantum wires and different error correction codes to form a quantum memory hierarchy.

This is joint work with Mark Oskin, Isaac Chuang, Dean Copsey, and John Kubiatowicz and conducted as part of the Quantum Architecture Research Center funded by the DARPA Quantum Information Science and Technology Program.

Frederic Chong is an Associate Professor and Chancellor's Fellow in the Department of Computer Science at the University of California at Davis. He received his PhD in 1996 from MIT and is a recipient of the National Science Foundation's CAREER award. His current research focuses on architectures and applications for novel computing technologies.

Refreshments will be served immediately following the talk in ECOT 831.

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University of Colorado Boulder
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