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Colloquium - Martínez

Speculative Shared-Memory Architectures
Department of Computer Science, University of Illinois at Urbana-Champaign
4/1/2002
2:00pm-3:00pm

Thread-Level Speculation (TLS), a.k.a. Speculative Parallelization, has emerged as a promising architectural technology to boost the performance of difficult-to-analyze codes. Under TLS, these codes are executed speculatively in parallel. The system provides a safety net, checking for dependence violations, and squashing and restarting offending threads on the fly.

In this talk I will present the two main contributions of my work to TLS. First, I propose a scalable multiprocessor architecture for TLS. We take a hierarchical approach that uses largely unmodified speculative chip-multiprocessors (CMPs) as building blocks. Because of its scalability, the resulting system achieves high speedups in important non-analyzable loops of several applications. Furthermore, its hierarchical structure successfully leverages future "commodity" speculative CMPs.

Second, I propose an application of TLS to overcome conservatively placed synchronization in parallel codes. Instead of waiting, threads execute speculatively past active barriers, taken locks, and unset flags. The proposed hardware solution is quite simple and it requires no programming effort, yet the performance improvements are very promising. We borrow the concept of "safe thread" from TLS to ensure that forward progress in the critical path is never compromised.

José F. Martínez is a PhD candidate in Computer Science at the University of Illinois at Urbana-Champaign. His research interests include parallel architectures for high performance and programmability, heterogeneous architectures, and hardware-software interaction.

Hosted by Daniel Connors.
Refreshments will be served immediately following the talk in ECOT 831.

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