home · mobile · calendar · colloquia · 1998-1999 · 

Colloquium - Austin

Scaling the Memory Wall: Technologies for Fast Memory Communication
Intel Microcomputer Research Labs
2/24/1999
9:00am-10:00am

As processor demands outpace memory, the performance of memory communication has become a critical component of good system performance. Future designs will face further degradations in memory performance brought on by architectural and technology trends that slow DRAM speed improvements, extend wire delays, and increase processor window sizes. To counter these trends, architects must endeavor to produce efficient communication mechanisms that exploit fast storage and present memory dependencies accurately and early in the processor pipeline.

In this talk, I will present two of my recent research efforts toward this goal. Memory Renaming is a microarchitecture-based technique that speeds the performance of speculative memory communication. It works by predicting memory communication early in the pipeline, and mapping the communication to fast registers. Cache-Conscious Data Placement is a compiler-based technique for reducing the frequency of data cache misses. The approach employs heuristic algorithms to find variable placement solutions that decrease inter-variable conflict, and increase cache line utilization and block prefetch.

Memory Renaming is joint work with Prof. Gary Tyson at University of Michigan. Cache-Conscious Data Placement is joint work with Prof. Brad Calder at University of California, San Diego.

Held jointly with the Department of Electrical and Computer Engineering.

Department of Computer Science
University of Colorado Boulder
Boulder, CO 80309-0430 USA
webmaster@cs.colorado.edu
www.cs.colorado.edu
May 5, 2012 (14:13)
XHTML 1.0/CSS2
©2012