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Colloquium - McKee

Dynamic Access Ordering for Streaming Computations
Intel Corporation
4/1/1998
3:00pm-4:00pm

Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal locality of reference that makes caches effective, they have predictable access patterns. Since most modern DRAM components support modes that make it possible to perform some access sequences faster than others, the predictability of the stream accesses makes it possible to reorder them to get better memory performance. We describe and evaluate (through simulation, mathematical analysis, and a prototype system) a Stream Memory Controller system that combines compile-time detection of streams with execution-time selection of the access order and issue. The SMC effectively prefetches read-streams, buffers write-streams, and reorders the accesses to exploit the existing memory bandwidth as much as possible.

The notion that performance of memory-intensive applications can be improved by reordering memory requests has been demonstrated before. Unique to our work is the premise that, for stream-like reference patterns, access ordering 1) should be performed to exploit both memory system architecture and device component capabilities, and 2) should be done at run-time, when more information is available on which to base scheduling decisions. Unlike other hardware prefetching or stream buffer designs, the SMC does not increase bandwidth requirements.

The SMC is practical to implement, using existing compiler technology and requiring only a modest amount of special-purpose hardware. With our prototype system, we have observed performance improvements for inner loops by factors of 13 over normal caching.

Department of Computer Science
University of Colorado Boulder
Boulder, CO 80309-0430 USA
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