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Colloquium - McKinley


Cooperative Caching: Hardware and Software Together at Last
University of Texas at Austin
Kathryn McKinley photo

Technology trends are exacerbating the memory system performance bottleneck. To achieve high performance on future microprocessors, new techniques must go well beyond the current minimalist load and store architecture/compiler interface. This talk demonstrates two cooperative approaches that bridge this gap: (1) cooperative cache replacement, and (2) guided prefetching. On a miss, cooperative cache replacement uses compiler hints to select replaced cache blocks in all levels of the cache hierarchy. Static compiler analysis marks loads without reuse, and significantly improves cache efficiency and total performance. Guided region prefetching (GRP) uses compiler hints to select which data will trigger hardware prefetching of large regions on a miss. GRP attains all the performance benefits of hardware prefetching but without its dramatic increases in memory fetch bandwidth. These results demonstrate significant promise for reducing the memory bottleneck using cooperative hardware/software technique.

Hosted by Amer Diwan.

The Department holds colloquia throughout the Fall and Spring semesters. These colloquia, open to the public, are typically held on Thursday afternoons, but sometimes occur at other times as well. If you would like to receive email notification of upcoming colloquia, subscribe to our Colloquia Mailing List. If you would like to schedule a colloquium, see Colloquium Scheduling.

Sign language interpreters are available upon request. Please contact Stephanie Morris at least five days prior to the colloquium.

See also:
Department of Computer Science
College of Engineering and Applied Science
University of Colorado Boulder
Boulder, CO 80309-0430 USA
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